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IS61LF25632T/D/J IS61LF25636T/D/J IS61LF51218T/D/J
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
FEATURES
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP and 119-pin PBGA package * Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0) * Snooze MODE for reduced-power standby * T version (three chip selects) * J version (PBGA Package with JTAG) * D version (two chip selects) * JTAG Boundary Scan for PBGA.
ISSI
OCTOBER 2002
(R)
DESCRIPTION
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance and memories for commucation and networking applications. The IS61LF25632 is organized as 262,144 words by 32 bits and the IS61LF25636 is organized as 262,144 words by 36 bits. The IS61LF51218 is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers that are controlled by a positive-edgetriggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 6.5 6.5 7.5 133 7.5 7.5 8.5 117 Units ns ns MHz
Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
1
www..com
IS61LF25632T/D/J IS61LF25636T/D/J
BLOCK DIAGRAM
IS61LF51218T/D/J
ISSI
A0'
(R)
MODE Q0
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
256K x 32; 256K x 36; 512K x 18 MEMORY ARRAY
Q 16/17 18/19
18/19 A D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
CE (T,D) CE2 (T,D) CE2 (T) D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
IS61LF51218T/D/J
ISSI
100-Pin TQFP (D Version)
A A CE CE2 BWd BWc BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A
(R)
119-pin PBGA (Top View) (D Version)
1 A VDDQ B NC C NC D DQc E DQc F VDDQ G DQc H DQc J VDDQ K DQd L DQd M VDDQ N DQd P DQd R NC T NC U VDDQ
2
3
4
5
6
7
A CE2 A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC A NC NC
A A A GND GND GND BWc GND NC GND BWd GND GND GND MODE A NC
ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC
A A A GND GND GND BWb GND NC GND BWa GND GND GND GND A NC
A A A NC DQb DQb DQb DQb VDD DQa DQa DQa DQa NC A NC NC
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A
NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC
256K x 32
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GW CE, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable
A CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
3
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
100-Pin TQFP (T Version)
IS61LF51218T/D/J
ISSI
(R)
NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A CE CE2 BWd BWc BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A
NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GW OE DQa-DQd MODE VDD GND VDDQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable CE, CE2, CE2 Synchronous Chip Enable
A CLK ADSP ADSC ADV BWa-BWd BWE
4
MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A
256K x 32
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
100-pin TQFP (T Version)
IS61LF51218T/D/J
ISSI
100-Pin TQFP (D Version)
A A CE CE2 BWd BWc BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A
(R)
A A CE CE2 BWd BWc BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A
DQPc DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa DQPa
DQPc DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd DQPd
MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO GW CE, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd
A CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A
256K x 36
JTAG Boundry Scan Pins Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
5
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
IS61LF51218T/D/J
PIN CONFIGURATION
ISSI
119-pin PBGA (Top View) (J Version)
1 A 2 3 4 5 6 7 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK
(R)
119-pin PBGA (Top View) (D Version)
1 A VDDQ B NC C NC D DQc E DQc F VDDQ G DQc H DQc J VDDQ K DQd L DQd M VDDQ N DQd P DQd R NC T NC U VDDQ NC NC NC NC NC VDDQ NC A A A NC ZZ A MODE VDD GND A NC DQPd GND A0 GND DQPa DQa DQd GND A1 GND DQa DQa DQd GND DQd DQd GND BWd CLK NC BWE GND BWa GND DQa DQa DQa DQa DQa VDDQ VDD NC VDD NC VDD VDDQ DQc GND DQc DQc GND BWc DQc GND DQPc GND NC CE OE ADV GW GND GND GND BWb GND DQPb DQb DQb DQb DQb DQb DQb VDDQ DQb DQb A A VDD A A NC CE2 A A A 2 3 4 5 6 7
ADSP ADSC
A A
A A
VDDQ
B
VDDQ NC C NC D DQc E DQc F VDDQ G DQc H DQc J VDDQ K DQd L DQd M VDDQ N DQd P DQd R NC T NC U VDDQ
A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC TMS
A A A GND GND GND BWc GND NC GND BWd GND GND GND MODE A TDI
A A A GND GND GND BWb GND NC GND BWa GND GND GND GND A TDO
A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
NC
256K x 36
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO GW CE, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd JTAG Boundry Scan Pins Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A CLK ADSP ADSC ADV BWa-BWd BWE
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
IS61LF51218T/D/J
ISSI
119-pin PBGA (Top View) (J Version)
1 A 2 3 4 5 6 7 VDDQ B NC C NC D DQb E NC F VDDQ G NC H DQb J VDDQ K NC L DQb M VDDQ N DQb P NC R NC T NC U VDDQ A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS A GND GND GND BWb GND NC GND GND GND GND GND MODE A TDI VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD NC TCK A GND GND GND GND GND NC GND BWa GND GND GND GND A TDO A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ CE2 A A A ADSP ADSC A A A A VDDQ NC
(R)
119-pin PBGA (Top View) (D Version)
1 A VDDQ B NC C NC D DQb E NC F VDDQ G NC H DQb J VDDQ K NC L DQb M VDDQ N DQb P NC R NC T NC U VDDQ NC NC NC NC NC VDDQ A A NC A A ZZ A MODE VDD GND A NC DQPb GND A0 GND NC DQa NC GND A1 GND DQa NC DQb GND NC GND NC BWE DQb GND CLK GND BWa GND NC DQa NC DQa NC VDDQ VDD NC VDD NC VDD VDDQ NC GND DQb NC GND BWb DQb GND NC GND NC CE OE ADV GW GND GND GND GND GND DQPa NC DQa NC DQa NC DQa VDDQ DQa NC A A VDD A A NC CE2 A A A 2 3 4 5 6 7
ADSP ADSC
A A
A A
VDDQ NC
512K x 18
512K x 18
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO GW CE, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd JTAG Boundry Scan Pins Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
7
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
100-Pin TQFP (D Version)
IS61LF51218T/D/J
ISSI
100-Pin TQFP (T Version)
A A CE CE2 NC NC BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A
(R)
A A CE CE2 NC NC BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A
NC NC NC VDDQ GND NC NC DQb DQb GND VDDQ DQb DQb GND VDD NC GND DQb DQb VDDQ GND DQb DQb DQPb NC GND VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A
A NC NC VDDQ GND NC DQPa DQa DQa GND VDDQ DQa DQa GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa NC NC GND VDDQ NC NC NC
NC NC NC VDDQ GND NC NC DQb DQb GND VDDQ DQb DQb GND VDD NC GND DQb DQb VDDQ GND DQb DQb DQPb NC GND VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A
A NC NC VDDQ GND NC DQPa DQa DQa GND VDDQ DQa DQa GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa NC NC GND VDDQ NC NC NC
512K x 18
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO GW CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd
512K x 18
JTAG Boundry Scan Pins Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A CLK ADSP ADSC ADV BWa-BWd BWE
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
TRUTH TABLE
Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
IS61LF51218T/D/J
ISSI
CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L H H L H H H H X X H X H H X X H X L X X L L X L L H H H H H H H H H H H H ADV X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D
(R)
Address Used CE None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L L L L X X H H X H X X H H X H
CE2 X X L X L H H H X X X X X X X X X X X X
PARTIAL TRUTH TABLE
Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
9
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
3rd Burst Address A1 A0 11 10 01 00
(R)
INTERLEAVED BURST ADDRESS TABLE (MODE = VDDQ or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN VDD Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vdd Supply Relatiive to GND
Value -55 to +150 1.6 100 -0.5 to VDDQ + 0.3 -0.5 to VDD + 0.5 -0.5 to 4.6
Unit C W mA V V V
10
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Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
OPERATING RANGE
Range Commercial Industrial
IS61LF51218T/D/J
ISSI
VDDQ 2.375-3.6V 2.375-3.6V
(R)
Ambient Temperature 0C to +70C -40C to +85C
VDD 3.3V, +10%, -5% 3.3V, +10%, -5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = -1.0 mA, VDDQ = 2.5V IOH = -4.0 mA, VDDQ = 3.3V IOL = 1.0 mA, VDDQ = 2.5V IOL = 8.0 mA, VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V GND VIN VDDQ(2) GND VOUT VDDQ, OE = VIH Com. Ind. Com. Ind. Min. 2.0 2.4 -- -- 1.7 2.0 -0.3 -0.3 -5 -5 -5 -5 Max. -- -- 0.4 0.4 VDD + 0.3 VDD + 0.3 0.7 0.8 5 5 5 5 Unit V V V V V V V V A A
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, All Inputs < VIL or > VIH OE = VIH, ZZ < VIL Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs < VIL or > VIH ZZ < VIL, f = fmax Device Deselected, VDD = Max., VIN GND + 0.2V or VDD -0.2V f=0 Com. Ind. 6.5 Max. 110 120 7.5 Max. 100 110 Unit mA mA
ISB
Standby Current
Com. Ind.
55 60
55 60
mA mA
ISBI
Standby Current CMOS Input
Com. Ind.
30 40
30 40
mA mA
Notes: 1. The MODE pin should be tied to VDD or GND. It exhibits 30 A maximum leakage current when tied to< GND + 0.2V or VDD - 0.2V.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
11
IS61LF25632T/D/J IS61LF25636T/D/J
CAPACITANCE(1,2)
Symbol CIN COUT Notes: Parameter
IS61LF51218T/D/J
ISSI
Max. 6 8 Unit pF pF
(R)
Conditions VIN = 0V VOUT = 0V
Input Capacitance Input/Output Capacitance
1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1ns 1.5V See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317
ZO = 50 OUTPUT 50
+3.3V
OUTPUT 351 5 pF Including jig and scope
1.5V
Figure 1
Figure 2
12
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
(R)
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1 ns 1.25V See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT 50
+2.5V
OUTPUT 1,538 5 pF Including jig and scope
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
13
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
6.5 Min. Max. -- 7.5 2.2 2.2 -- 2 0 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 133 -- -- -- 6.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- 7.5 Min. Max. -- 8.5 2.5 2.5 -- 2 0 -- -- 0 -- 1.8 1.8 1.8 1.8 1.8 0.5 0.5 0.5 0.5 0.5 117 -- -- -- 7.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol fMAX tKC tKH tKL tKQ tKQX
(1)
Parameter Clock Frequency Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
tKQLZ(1,2) tKQHZ(1,2) tOEQ tOELZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH Note:
(1,2)
tOEHZ(1,2)
1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2.
14
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IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
ADSP is blocked by CE inactive
(R)
READ/WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP
tSS tSH
ADSC
ADV
tAS tAH
A
RD1
tWS tWH
WR1
RD2
RD3
GW
tWS tWH
BWE
tWS tWH
BWd-BWa
tCES tCEH
WR1 CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE2
tCES tCEH
Unselected with CE2
CE2
tOEHZ
OE
tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
tKQX tKQHZ
2a
2b
2c
2d
tKQHZ
DATAIN
High-Z
tDS
1a
tDH
Single Read Flow-through
Single Write
Burst Read
Unselected
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IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
6.5 Min. Max. 7.5 2.0 2.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7.5 Min. Max. 8.5 2.5 2.5 1.8 1.8 1.8 1.8 1.8 1.8 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Parameter Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
16
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WRITE CYCLE TIMING
IS61LF51218T/D/J
ISSI
ADSP is blocked by CE1 inactive
(R)
tKC
CLK
tSS tSH tKH tKL
ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
A17-A0
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BWd-BWa
tCES tCEH
WR1
WR2 CE1 Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE
DATAOUT
High-Z
tDS tDH
DATAIN
High-Z
1a
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d
3a
Single Write
Burst Write
Write
Unselected
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17
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
Min. Com. Ind. -- -- 2 2 2 0 Max. 30 40 -- -- -- -- Unit mA cycle cycle cycle ns ZZ VIH ZZ VIH
(R)
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions
SLEEP MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
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IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
Test Access Port (TAP) - Test Clock Test Mode Select (TMS)
(R)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The IS61LF25636T/D/J and IS61LF51218T/D/JT/D/JT/D/ J have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package or with the IS61LPS25632T/D/J.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.
Disabling the JTAG Feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (GND) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.
TAP CONTROLLER BLOCK DIAGRAM
0 Bypass Register
2 TDI Selection Circuitry
1
0 Selection Circuitry TDO
Instruction Register
31 30 29
...
2
1
0
Identification Register
x
.....
Boundary Scan Register*
2
1
0
TCK TMS
TAP CONTROLLER
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IS61LF25632T/D/J IS61LF25636T/D/J
Test Data Out (TDO)
IS61LF51218T/D/J
Boundary Scan Register
ISSI
(R)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 51 Bit Size (x36) 3 1 32 70
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (GND) when the BYPASS instruction is executed.
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IS61LF51218T/D/J
ISSI
(R)
IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID REGISTER CONTENTS
Presence Register
Die Revision Code
Part Configuration
Vendor Defomotopm
ISSI Technology JEDEC Vendor ID Code 7 1 1 654 010 010 32 10 10 1 1 1
Part # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 256K X X X X 0 0 1 1 0 0 0 1 0 0 X X X X X X 0 0 0 1 512K X X X X 0 0 1 1 1 0 0 0 1 1 X X X X X X 0 0 0 1
0 1 1
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the CaptureDR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). To insure that the SRAM
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for future use. Do not use these instructions.
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21
IS61LF25632T/D/J IS61LF25636T/D/J
INSTRUCTION CODES
Code 001 010 011 100 Instruction IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD
IS61LF51218T/D/J
ISSI
(R)
Description Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
101 110 111
RESERVED RESERVED BYPASS
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset 1 0 Run Test/Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 1 Select IR 0 1 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 0 Exit2 IR 1 1
0 1
0 1
Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0
0
1
Update IR 0
22
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
Min. 1.7 2.1 -- -- 1.7 IOLT = 2mA -0.3 -5 Max. -- -- 0.7 0.2 VDD +0.3 0.7 5 IOH = -2.0 mA IOH = -100 mA IOL = 2.0 mA IOL = 100 mA V V V V V V mA
(R)
TAP ELECTRICAL CHARACTERISTICS Over the Operating Range(1,2)
Symbol VOH1 VOH2 VOL1 VOL2 VIH VIL IX Notes:
1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) VDD +1.5V for t tTCYC/2, Undershoot:VIL (AC) 0.5V for t tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current
Test Conditions
Units
GND V I VDDQ
TAP AC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol tTCYC fTF tTH tTL tTMSS tTDIS tCS tTMSH tTDIH tCH tTDOV tTDOX Notes:
1. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Parameter TCK Clock cycle time TCK Clock frequency TCK Clock HIGH TCK Clock LOW TMS setup to TCK Clock Rise TDI setup to TCK Clock Rise Capture setup to TCK Rise TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture hold after Clock Rise TCK LOW to TDO valid TCK LOW to TDO invalid
Min. 100 -- 40 40 10 10 10 10 10 10 -- 0
Max. -- 10 -- -- -- -- -- -- -- -- 20 --
Unit ns MHz ns ns ns ns ns ns ns ns ns ns
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23
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
TAP OUTPUT LOAD EQUIVALENT
(R)
TAP AC TEST CONDITIONS
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage 0 to 2.5V 1ns 1.25V 1.25V 1.25V
50 1.25V
TDO Z0 = 50 20 pF GND
TAP TIMING
1 tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 2 tTLTH tTHTL 3 4 5 6
24
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Signal Bump Name ID BWa BWb BWc BWd CE2 CE A A DQc DQc DQc DQc DQc DQc DQc DQc DQc NC 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R Bit # 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE A A A A A1 A0 2K 1L 2M 1N 1P 1K 2L 2N 2P 3R 2C 3C 5C 6C 4N 4P
(R)
BOUNDARY SCAN ORDER (256K X 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Bump Name ID A A A A A A A DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal Bump Name ID DQb DQb DQb DQb DQb DQb DQb DQb A A ADV ADSP ADSC OE BWE GW CLK A 7G 6F 7E 7D 7H 6G 6E 6D 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B Signal Bump Name ID
BOUNDARY SCAN ORDER (512K X 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 Signal Bump Name ID A A A A A A A DQa DQa DQa DQa ZZ DQa 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H Bit # 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Bump Name ID DQa DQa DQa DQa A A A ADV ADSP ADSC OE BWE GW 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 Signal Bump Name ID CLK A BWa BWb CE2 CE A A DQb DQb DQb DQb NC 4K 6B 5L 3G 2B 4E 3A 2A 1D 2E 2G 1H 5R Bit # 40 41 42 43 44 45 46 47 48 49 50 51 Signal Bump Name ID DQb DQb DQb DQb DQb MODE A A A A A1 A0 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
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25
IS61LF25632T/D/J IS61LF25636T/D/J
IS61LF51218T/D/J
ISSI
Industrial Range: -40C to +85C
Speed 6.5 ns 7.5 ns Order Part Number IS61LF25632T-6.5TQI IS61LF25632D-6.5TQI IS61LF25632T-7.5TQI IS61LF25632D-7.5TQI Package TQFP TQFP TQFP TQFP
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 6.5 ns 7.5 ns Order Part Number IS61LF25632T-6.5TQ IS61LF25632D-6.5TQ IS61LF25632T-7.5TQ IS61LF25632D-7.5TQ IS61LF25632D-7.5B Package TQFP TQFP TQFP TQFP PBGA
Industrial Range: -40C to +85C Commercial Range: 0C to +70C
Speed 6.5 ns Order Part Number IS61LF25636T-6.5TQ IS61LF25636D-6.5TQ IS61LF25636D-6.5B IS61LF25636J-6.5B IS61LF25636T-7.5TQ IS61LF25636D-7.5TQ IS61LF25636D-7.5B IS61LF25636J-7.5B Package TQFP TQFP PBGA PBGA TQFP TQFP PBGA PBGA Speed 6.5 ns 7.5 ns Order Part Number IS61LF25636T-6.5TQI IS61LF25636D-6.5TQI IS61LF25636T-7.5TQI IS61LF25636D-7.5TQI IS61LF25636D-7.5BI IS61LF25636J-7.5BI Package TQFP TQFP TQFP TQFP TQFP TQFP
7.5 ns
Industrial Range: -40C to +85C
Speed Order Part Number IS61LF51218T-6.5TQI IS61LF51218D-6.5TQI IS61LF51218T-7.5TQI IS61LF51218D-7.5TQI IS61LF51218D-7.5BI IS61LF51218J-7.5BI Package TQFP TQFP TQFP TQFP TQFP TQFP
Commercial Range: 0C to +70C
Speed 6.5 ns Order Part Number IS61LF51218T-6.5TQ IS61LF51218D-6.5TQ IS61LF51218D-6.5B IS61LF51218J-6.5B IS61LF51218T-7.5TQ IS61LF51218D-7.5TQ IS61LF51218D-7.5B IS61LF51218J-7.5B Package TQFP TQFP PBGA PBGA TQFP TQFP PBGA PBGA
6.5 ns 7.5 ns
7.5 ns
26
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02

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